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Features
* One-Time Programmable (OTP) Feature * Low-Voltage and Standard-Voltage Operation
- 5.0 (VCC = 4.5V to 5.5V) - 2.7 (VCC = 2.7V to 5.5V) - 1.8 (VCC = 1.8V to 3.6V) Internally Organized 16,384 x 8 and 32,768 x 8 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility Write Protect Pin for Hardware and Software Data Protection 64-Byte Page Write Mode (Partial Page Writes Allowed) Self-Timed Write Cycle (5 ms typical) High Reliability - Endurance: 100,000 Write Cycles - Data Retention: 40 Years - ESD Protection: >4000V Automotive Grade and Extended Temperature Devices Available 8-Pin JEDEC PDIP and 8-Pin JEDEC and EIAJ SOIC Packages
* * * * * * * * *
* *
2-Wire Serial EEPROMs with Permanent Software Write Protect
128K (16,384 x 8) 256K (32,768 x 8)
Description
The AT24CS128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device's cascadable feature allows up to 4 devices to share a common 2-wire bus. The device also features a one-time programmable 2048 bit array, which once enabled, becomes read-only and cannot be overwritten. If not enabled, the OTP section will function as part of the normal memory array. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP (AT24CS128/256), 8-pin EIAJ (AT24CS128/256), 8-pin JEDEC SOIC (AT24CS128) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Pin Configurations
Pin Name A0 to A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect
A0 A1 A2 GND
8-Pin PDIP
1 2 3 4 8 7 6 5 VCC WP SCL SDA
AT24CS128 AT24CS256 with Permanent Software Write Protect Advanced Information
8-Pin SOIC
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
Rev. 1152A-09/98
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Absolute Maximum Ratings*
Operating Temperature .................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage........................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Block Diagram
A2
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with AT24C32/64. When the pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A1 and A0 are zero. The A2 device address input is a "don't care" input. WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write protect function.
Memory Organization
AT24CS128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as 256/512 pages of 64bytes each. Random word addressing requires a 14/15-bit data word address.
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AT24CS128/256
AT24CS128/256
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V.
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, SCL) This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Standby Current (2.7V option) Standby Current (5.0V option) Input Leakage Current Output Leakage Current Input Low Level
(Note:)
Test Condition
Min 1.8 2.7 4.5
Typ
Max 3.6 5.5 5.5
Units V V V mA mA A A
VCC = 5.0V VCC = 5.0V VCC = 1.8V VCC = 3.6V VCC = 2.7V VCC = 5.5V VCC = 4.5 - 5.5V
READ at 400 kHz WRITE at 400 kHz VIN = VCC or VSS
1.0 2.0
2.0 3.0 0.2 2.0 0.5
ISB2 ISB3 ILI ILO VIL VIH VOL2 VOL1 Note:
VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS -0.6 VCC x 0.7 0.10 0.05
5.0 5.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 A A A V V V V
Input High Level(Note:) Output Low Level Output Low Level VCC = 3.0V VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA
VIL min and VIH max are reference only and are not tested
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AC Characteristics
Applicable over recommended operating range from TA = -40C to +85C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.8-volt Symbol fSCL tLOW tHIGH tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Notes: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time Inputs Fall Time
(1)
2.7-volt Min Max 1000 0.6 0.4
5.0-volt Min Max 1000 0.6 0.4 Units kHz s s 0.55 s s s s s ns 0.3 100 0.25 50 s ns s ns 10 100K ms Write Cycles
Min
Max 400
1.3 1.0 0.1 1.2 0.6 0.6 0 100 0.3 300 0.6 50 20 100K 0.9
0.05 0.5 0.25 0.25 0 100
0.55
0.05 0.5 0.25 0.25 0 100
0.3 100 0.25 50 10 100K
(1)
Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Page Mode
1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3K (2.7V, 5V), 10K (1.8V) Input pulse voltages: 0.3VCC to 0.7VCC Input rise and fall times: 50ns Input and output timing reference voltages: 0.5VCC
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24CS128/256 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
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AT24CS128/256
AT24CS128/256
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
8th BIT WORD n
ACK tWR STOP CONDITION
(1)
START CONDITION
Note:
1.
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5
Data Validity
Start and Stop Definition
Output Acknowledge
6
AT24CS128/256
AT24CS128/256
Device Addressing
The 128K/256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2-wire EEPROM devices. The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. DATA SECURITY: The AT24CS128/256 has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at VCC. than 64 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.
OTP Description/Operation
The OTP feature provides the user with a 2048-bit (256 x 8) security section, which once programmed and enabled, becomes read-only and data cannot be changed or overwritten. The OTP section is located in the upper 2K section of the memory array in the AT24CS128/256. If not enabled, the OTP section will function as part of the normal memory array. To enable the OTP section: 1. Inputs must be connected: A2 = Don't Care, A1 and A0 = VCC or GND 2. Initiate the programming sequence:
START 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx STOP
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2). PAGE WRITE: The 128K/256K EEPROM is capable of 64byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3). The data word address lower 6 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more
Once enabled, previously written data cannot be changed. The status of the OTP section can only be confirmed by initiating a programming sequence to the OTP section and verifying by a read command. The use of the write protect (WP) feature can be utilized with or without enabling the OTP function.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). 7
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5). Figure 1. Device Address
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6).
Figure 2. Byte Write
Figure 3. Page Write
(* = DON'T CARE bit) ( = DON'T CARE bit for the 128K)
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AT24CS128/256
AT24CS128/256
Figure 4. Current Address Read
Figure 5. Random Read
(* = DON'T CARE bit) ( = DON'T CARE bit for the 128K) Figure 6. Sequential Read
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AT24CS128 Ordering Information
tWR (max) (ms) 10 ICC (max) (A) 3000 ISB (max) (A) 5.0 fMAX (kHz) 1000 Ordering Code AT24CS128-10PC AT24CS128N-10SC AT24CS128W-10SC AT24CS128-10PI AT24CS128N-10SI AT24CS128W-10SI AT24CS128-10PC-2.7 AT24CS128N-10SC-2.7 AT24CS128W-10SC-2.7 AT24CS128-10PI-2.7 AT24CS128N-10SI-2.7 AT24CS128W-10SI-2.7 AT24CS128-10PC-1.8 AT24CS128N-10SC-1.8 AT24CS128W-10SC-1.8 AT24CS128-10PI-1.8 AT24CS128N-10SI-1.8 AT24CS128W-10SI-1.8 Package 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
3000
5.0
1000
10
1500
0.5
400
1500
0.5
400
20
800
0.2
100
800
0.2
100
Package Type 8P3 8S1 8S2 Blank -2.7 -1.8 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Standard Operation (4.5V to 5.5V) Low-Voltage (2.7V to 5.5V) Low-Voltage (1.8V to 3.6V)
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AT24CS128/256
AT24CS128/256
AT24CS256 Ordering Information
tWR (max) (ms) 10 ICC (max) (A) 3000 3000 10 1500 1500 20 800 800 ISB (max) (A) 5.0 5.0 0.5 0.5 0.2 0.2 fMAX (kHz) 1000 1000 400 400 100 100 Ordering Code AT24CS256-10PC AT24CS256W-10SC AT24CS256-10PI AT24CS256W-10SI AT24CS256-10PC-2.7 AT24CS256W-10SC-2.7 AT24CS256-10PI-2.7 AT24CS256W-10SI-2.7 AT24CS256-10PC-1.8 AT24CS256W-10SC-1.8 AT24CS256-10PI-1.8 AT24CS256W-10SI-1.8 Package 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 8P3 8S2 Blank -2.7 -1.8 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Standard Operation (4.5V to 5.5V) Low-Voltage (2.7V to 5.5V) Low-Voltage (1.8V to 3.6V)
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AT24CS128/256
Packaging Information
8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters)
.400 (10.16) .355 (9.02) PIN 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690)
.020 (.508) .013 (.330)
PIN 1
.157 (3.99) .150 (3.81)
.244 (6.20) .228 (5.79)
.300 (7.62) REF
.050 (1.27) BSC
.100 (2.54) BSC
.210 (5.33) MAX SEATING PLANE .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14)
.196 (4.98) .189 (4.80)
.015 (.380) MIN .022 (.559) .014 (.356)
.068 (1.73) .053 (1.35)
.010 (.254) .004 (.102)
.325 (8.26) .300 (7.62)
.012 (.305) .008 (.203)
0 REF 15 .430 (10.9) MAX
0 REF 8 .050 (1.27) .016 (.406)
.010 (.254) .007 (.203)
8S2, 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters)
.020 (.508) .012 (.305)
PIN 1
.213 (5.41) .205 (5.21)
.330 (8.38) .300 (7.62)
.050 (1.27) BSC
.212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78)
.013 (.330) .004 (.102) 0 REF 8 .035 (.889) .020 (.508) .010 (.254) .007 (.178)
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